|
发表于 2023-9-25 19:36:31
|
显示全部楼层
`timescale 1ns/1ns
module JC_counter(
input clk ,
input rst_n,
output reg [3:0] Q
);
reg flag;
reg [2:0] cnt;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
flag <= 1;
cnt <= 0;
Q <= 0;
end else begin
if (cnt == 4)
cnt <= 1;
else
cnt <= cnt + 1;
if (cnt == 4)
flag <= ~flag;
Q <= (flag) ? {1'b1, Q[3:1]} : {1'b0, Q[3:1]};
end
end
endmodule |
|